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application note r01an0459ej0200 rev. 2.00 page 1 of 43 2014.03.24 rl78/g13 serial array unit (uart communication) introduction this application note explains how to use uart communication through the serial array unit (sau). ascii characters transmitted from the device on the opposite side are analyzed to make responses. target device rl78/g13 when applying the sample program covered in this application note to another microcomputer, modify the program according to the specifications for the target microcomputer and conduct an extensive evaluation of the modified program. r01an0459ej0200 rev. 2.00 2014.03.24
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 2 of 43 2014.03.24 contents 1. specifications ................................................................................................................ .................... 3 2. operation chec k conditions .................................................................................................... ......... 5 3. related applic ation no te ...................................................................................................... ............. 5 4. description of the hardware ................................................................................................... ........... 6 4.1 hardware configur ation example ................................................................................................ ..... 6 4.2 list of pins to be used ....................................................................................................... ............... 6 5. description of the software ................................................................................................... ............ 7 5.1 operation outline ............................................................................................................. ................. 7 5.2 list of option byte settings .................................................................................................. ............. 8 5.3 list of constants ............................................................................................................................... . 8 5.4 list of va riables ............................................................................................................. .................... 8 5.5 list of functions ............................................................................................................. ................... 9 5.6 function specifications ....................................................................................................... .............. 9 5.7 flowcharts .................................................................................................................... ................... 12 5.7.1 initializati on function ....................................................................................................... .......... 12 5.7.2 system function ............................................................................................................... ......... 13 5.7.3 i/o port setup ................................................................................................................ ............ 14 5.7.4 cpu clock setup ............................................................................................................... ........ 15 5.7.5 serial array unit setup ....................................................................................................... ....... 16 5.7.6 uart0 setup ................................................................................................................... .......... 18 5.7.7 main function ................................................................................................................. ........... 29 5.7.8 uart0 reception status in itialization function ........................................................................ 31 5.7.9 uart0 operation st art function ............................................................................................... 32 5.7.10 intsr0 interrupt se rvice routine .......................................................................................... 36 5.7.11 uart0 receive data classi fication function ........................................................................ 37 5.7.12 uart0 data transmis sion function ...................................................................................... 38 5.7.13 uart0 reception error in terrupt function ............................................................................ 39 5.7.14 uart0 reception er ror classification function .................................................................... 40 5.7.15 intst0 interrupt se rvice routine .......................................................................................... 41 5.7.16 uart0 transmission end pr ocessing function .................................................................... 42 6. sample code ............................................................................................................................... .... 43 7. documents for reference ....................................................................................................... ........ 43 revision re cord ............................................................................................................... ....................... 44 general precautions in the h andling of mpu/mc u products ................................................................. 45
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 3 of 43 2014.03.24 1. specifications in this application note, uart communication is performe d through the serial array unit (sau). ascii characters transmitted from the device on the opposite side are analyzed to make responses. table 1.1 shows the peripheral function to be used and its use. figures 1.1 and 1.2 illustrate uart communication operation. table 1.1 peripheral function to be used and its use peripheral function use serial array unit 0 perform uart communication using the txd0 pin (transmission) and the rxd0 pin (reception). figure 1.1 uart reception timing chart st permit operation of uart receive data p sp reception & shift operation receive data permit start of uart communication shift register 01 reception completed sauen rxd0 pin intsr0 tsf01 ss01 se01 sdr01 st: start bit p: parity bit sp: stop bit
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 4 of 43 2014.03.24 figure 1.2 uart transmission timing chart st permit operation of uart transmit data p sp shift operation transmit data permit start of uart communication transfer completed st: start bit p: parity bit sp: stop bit sauen txd0 pin intst0 tsf00 ss00 se00 sdr00 shift re g ister 00
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 5 of 43 2014.03.24 2. operation check conditions the sample code contained in this application note has been checked under the conditions listed in the table below. table 2.1 operation check conditions item description microcontroller used rl78/g13 (r5f100lea) operating frequency ? high-speed on-chip oscillator (hoco) clock: 32 mhz ? cpu/peripheral hardware clock: 32 mhz operating voltage 5.0 v (can run on a voltage range of 2.9 v to 5.5 v.) lvd operation (v lvi ): reset mode 2.81 v (2.76 v to 2.87 v) integrated development environment (cubesuite+) cubesuite + v1.00.01 c compiler (cubesuite+) ca78k0r v1.20 integrated development environment (e2studio) e2studio v2.0.1.3 c compiler (e2studio) kpit gnurl78-elf toolchain v13.02 integrated development environment (iar) iar embedded workbench for renesas rl78 v1.30.2 c compiler (iar) iar c/c++ compiler fo r renesas rl78 v1.30.2.50607 3. related application note the application note that is related to this a pplication note is listed below for reference. rl78/g13 initialization (r01an0451ej0100) application note
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 6 of 43 2014.03.24 4. description of the hardware 4.1 hardware configuration example figure 4.1 shows an example of hardware configuration that is used for this application note. figure 4.1 hardware configuration caution: 1. the purpose of this circuit is only to provide the connection outline and the circuit is simplified accordingly. when designing and implementing an actua l circuit, provide proper pin treatment and make sure that the hardware's electrical specifications are met (connect the input-only ports separately to v dd or v ss via a resistor). 2. connect any pins whose name begins with ev ss to v ss and any pins whose name begins with ev dd to v dd , respectively. 3. v dd must be held at not lower than the reset release voltage (v lvi ) that is specified as lvd. 4.2 list of pins to be used table 4.1 lists the pins to be used and their function. table 4.1 pins to be used and their functions pin name i/o description p12/so00/txd0/tooltxd output data transmission pin p11/si00/rxd0/toolrxd/sda00 input data reception pin reset v dd rl78/g13 ev dd v dd v dd ev ss v ss regc rxd0 txd0 device on the opposite side transmission reception p40/tool0 for on-chip debugger
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 7 of 43 2014.03.24 5. description of the software 5.1 operation outline this sample code transmits, to the devi ce on the opposite side, the data corresp onding to that received from the device. if an error occurs, it transmits to the device the data co rresponding to the error. tables 5.1 and 5.2 show the correspondence between tran smit data and receive data. table 5.1 correspondence between receive data and transmit data receive data response (transmit) data t (54h) o (4fh), k (4bh), ?cr? (0dh), ?lf? (0ah) t (74h) o (6fh), k (6bh), ?cr? (0dh), ?lf? (0ah) other than above u (55h), c (43h), ?cr? (0dh), ?lf? (0ah) table 5.2 correspondence between error and transmit data error response (transmit) data parity error p (50h), e (45h ), ?cr? (0dh), ?lf? (0ah) framing error f (46h), e (45h), ?cr? (0dh), ?lf? (0ah) overrun error o (4fh), e (45h ), ?cr? (0dh), ?lf? (0ah) (1) perform initial setting of uart. ? use sau0 channels 0 and 1 as uart. ? use the p12/txd0 pin and the p11/rxd0 pin for data output and data input, respectively. ? the data length is 8 bits. ? set the data transfer direction to lsb first. ? use even parity as the parity setting. ? set the receive data level to standard. ? set the transfer rate to 9600 bps. ? use reception end interrupt (intsr0), transmission end interrupt (intst0), and er ror interrupt (intsre0). ? set the interrupt priority orders of ints r0, intst0, and intsre0 to low priority. (2) after the system is made to enter a uart communicati on wait state by using the serial channel start register, a halt instruction is executed. processi ng is performed in response to reception end interrupt (intsr0) and error interrupt (intsre0). ? when an intsr0 occurs, the received data is taken in and the data corresponding to the received data is transmitted. when an intsre0 occurs, error handling is pe rformed to transmit the data corresponding to the error. ? after data transmission, a halt instru ction is executed again to wait for reception end interru pt (intsr0) and error interrupt (intsre0).
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 8 of 43 2014.03.24 5.2 list of option byte settings table 5.1 summarizes the settings of the option bytes. table 5.1 option byte settings 5.3 list of constants table 5.2 lists the constants that are used in this sample program. table 5.2 constants for the sample program constant setting description messageok[4] "okrn" response message to reception of ?t?. messageok[4] "okrn" response message to reception of ?t?. messageuc[4] "ucrn" response message to reception of characters other than ?t? or ?t?. messagefe[4] "fern" response message to a framing error. messagepe[4] "pern" response message to a parity error. messageoe[4] "oern" response message to an overrun error. 5.4 list of variables table 5.3 lists the global variable that is used by this sample program. table 5.3 global variable type variable name contents function used uint8_t g_uart0rxbuf receive data buffer main() uint8_t gp_uart0txaddress transmit data pointer r_uart0_send, r_uart0_interrupt_send uint16_t g_uart0txcnt transmit data number counter r_uart0_send, r_uart0_interrupt_send uint8_t gp_uart0rxaddress receive data pointer r_uart0_receive, r_uart0_interrupt_receive, r_uart0_interrupt_error uint16_t g_uart0rxcnt receive data number counter r_uart0_receive, r_uart0_interrupt_receive uint16_t g_uart0rxlen receive data number r_uart0_receive, r_uart0_interrupt_receive address value description 000c0h/010c0h 01101110b disables the watchdog timer. (stops counting after the re lease from the reset state.) 000c1h/010c1h 01111111b lvd reset mode, 2.81 v (2.76 v to 2.87 v) 000c2h/010c2h 11101000b hs mode, hoco: 32 mhz 000c3h/010c3h 10000100b enables the on-chip debugger.
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 9 of 43 2014.03.24 5.5 list of functions table 5.4 lists the functions that are used in this sample program. table 5.4 functions function name outline r_uart0_start uart0 operation start r_uart0_receive uart0 reception status initialization function r_uart0_send uart0 data transmission function r_uart0_interrupt_receive uart0 reception end interrupt handling r_uart0_callback_receiveend uart0 receive data classification function r_uart0_interrupt_error uart 0 error interrupt handling r_uart0_callback_error uart0 reception error classification function r_uart0_interrupt_send uart0 tr ansmission end interrupt handling r_uart0_callback_sendend uart0 transmission end processing function 5.6 function specifications this section describes the specifications for the functions that are used in this sample program. [function name ]r_ uart0_start synopsis uart0 operation start header r_cg_macrodriver.h, r_cg_ser ial.h, and r_cg_userdefine.h declaration void r_ uart0_start(void) explanation starts operation of channel 0 of serial arra y units 0 and 1 to make the system enter a communication wait state. arguments none return value none remarks none [function name] r_uart0_receive synopsis uart0 reception status initialization function header r_cg_macrodriver.h, r_ cg_serial.h, r_cg_userdefine.h declaration md_status r_uart0_receive(uint8_t *rxbuf, uint16_t rxnum) explanation makes initial setting for uart0 reception. arguments uint8_t *rxbuf : [receive data buffer address] uint16_t rxnum : [receive data buffer size] return value [md_ok]: rec eption setting is completed [md_argerror]: recept ion setting failed remarks none
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 10 of 43 2014.03.24 [function name] r_uart0_send synopsis uart0 data transmission function header r_cg_macrodriver.h, r_cg_s erial.h, r_cg_userdefine.h declaration md_status r_uart0_send(uint8_t* txbuf, uint16_t txnum) explanation makes initial setting for uart0 transmission, and starts data transmission. arguments uint8_t *txbuf : [transmit data buffer address] uint16_t txnum : [transmit data buffer size] return value [md_ok]: transmi ssion setting is completed [md_argerror]: transmi ssion setting failed remarks none [function name] r_uart0_interrupt_receive synopsis uart0 reception end interrupt handling header r_cg_macrodriver.h, r_cg_ser ial.h, and r_cg_userdefine.h declaration __interrupt void r_uart0_interrupt_receive(void) explanation makes a response (data transmission) corresponding to received data. arguments none return value none remarks none [function name ]r_uart0_interrupt_error synopsis uart error interrupt function header r_cg_macrodriver.h, r_cg_ser ial.h, and r_cg_userdefine.h declaration __interrupt void r_uart0_interrupt_error(void) explanation transmits the data corresponding to a detected error. arguments none return value none remarks none [function name ] r_uart0_callback_receiveend synopsis uart0 receive data classification function header r_cg_macrodriver.h, r_cg_ser ial.h, and r_cg_userdefine.h declaration void r_uart0_callback_receiveend(void) explanation clears the reception error flag. arguments none return value none remarks none [function name] r_uart0_callback_error synopsis uart0 reception error classification function header r_cg_macrodriver.h, r_cg_ser ial.h, and r_cg_userdefine.h declaration void r_uart0_callback_error(uint8_t err_type) explanation makes flag setting for transmission of the data corresponding to an error. arguments err_type : error type return value none remarks none
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 11 of 43 2014.03.24 [function name] r_uart0_interrupt_send synopsis uart0 transmission end interrupt handling header r_cg_macrodriver.h, r_cg_ser ial.h, and r_cg_userdefine.h declaration __interrupt void r_uart0_interrupt_send(void) explanation transmits a specified number of pieces of data. arguments none return value none remarks none [function name] r_uart0_callback_sendend synopsis uart0 transmission end processing function header r_cg_macrodriver.h, r_cg_s erial.h, r_cg_userdefine.h declaration void r_uart0_callback_sendend(void) explanation makes transmission end flag setting. arguments none return value none remarks none
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 12 of 43 2014.03.24 5.7 flowcharts figure 5.1 shows the overall flow of the sample program described in this application note. figure 5.1 overall flow 5.7.1 initialization function figure 5.2 shows the flowchart for the initialization function. figure 5.2 initialization function note: this function is used in the renesas cubesui te+ sample code. the function __low_level_init initializes the system in the iar workbench ide-based sample code instead. 0 1 ie ? ?
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 13 of 43 2014.03.24 5.7.2 system function figure 5.3 shows the flowchart for the system function. figure 5.3 system function r_systeminit() return r_port_create () r_cgc_create () r_sau0_create() set up i/o ports disuse peripheral i/o redirection function set up cpu clock set up serial array unit pior register ?
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 14 of 43 2014.03.24 5.7.3 i/o port setup figure 5.4 shows the flowchart for setting up the i/o ports. figure 5.4 i/o port setup note: refer to the section entitled "flowcharts" in rl78/g13 initialization application note (r01an0451ej0100) for the configuration of the unused ports. caution: provide proper treatment for unused pins so that their electrical specifications ar e observed. connect each of any unused input-only ports to v dd or v ss via a separate resistor. r_port_create() return set the pins other than p11 and p12 to output port. set the output latch of all ports to low. pm1 register ?
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 15 of 43 2014.03.24 5.7.4 cpu clock setup figure 5.5 shows the flowchart for setting up the cpu clock. figure 5.5 cpu clock setup caution: for details on the procedure for setting up the cpu clock (r_cgc_create ()), refer to the section entitled "flowcharts" in rl78/g13 initialization application note (r01an0451ej0100). r_cgc_create() return cmc register ? ? 1 xtstop bit ? 1 set up high-speed system clock/subsystem clock select cpu/peripheral hardware clock (f clk ) mcm0 bit ? ? 0: selects main system clock (f main ) as cpu/peripheral hardware clock ( f clk ) .
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 16 of 43 2014.03.24 5.7.5 serial array unit setup figure 5.6 shows the flowchart for setting up the serial array unit. figure 5.6 serial array unit setup r_sau0_create() return supply input clock to serial array unit 0 set ck00 and ck01 to 2 mhz r _ uart0 _ create() sau0en bit ? 1 sps0 register ? 44h set uart0
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 17 of 43 2014.03.24 symbol: sps0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 prs 013 prs 012 prs 011 prs 010 prs 003 prs 002 prs 001 prs 000 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 bits 7 to 0 prs 0n3 prs 0n2 prs 0n1 prs 0n0 operation clock (ck00) selection (n = 0, 1) f clk = 2 mhz f clk = 5 mhz f clk = 10 mhz f clk = 20 mhz f clk = 32 mhz 0 0 0 0 f clk 2 mhz 5 mhz 10 mhz 20 mhz 32 mhz 0 0 0 1 f clk /2 1 mhz 2.5 mhz 5 mhz 10 mhz 16 mhz 0 0 1 0 f clk /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 8 mhz 0 0 1 1 f clk /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 4 mhz 0 1 0 0 f clk /2 4 125 khz 312.5 khz 625 khz 1.25 mhz 2 mhz 0 1 0 1 f clk /2 5 62.5 khz 156.2 khz 312.5 khz 625 khz 1 mhz 0 1 1 0 f clk /2 6 31.25 khz 78.1 khz 156.2 khz 312.5 khz 500 khz 0 1 1 1 f clk /2 7 15.62 khz 39.1 khz 78.1 khz 156.2 khz 250 khz 1 0 0 0 f clk /2 8 7.81 khz 19.5 khz 39.1 khz 78.1 khz 125 khz 1 0 0 1 f clk /2 9 3.91 khz 9.76 khz 19.5 khz 39.1 khz 62.5 khz 1 0 1 0 f clk /2 10 1.95 khz 4.88 khz 9.76 khz 19.5 khz 31.25 khz 1 0 1 1 f clk /2 11 977 hz 2.44 khz 4.88 khz 9.76 khz 15.6 khz other than above. setting prohibited. caution: for details on the register setup procedures, refer to rl78/g13 user's manual: hardware. ? peripheral enable register 0 (per0) clock supply start supplying clock to the sau symbol: per0 7 6 5 4 3 2 1 0 rtcen iica1en adcen iica0en sau1en sau0en tau1en tau0en x 0 x x x 1 0 x bit 2 sau0en input clock control for serial array unit 0 0 stops supply of input clock. 1 starts supply of input clock. caution: for details on the register setup procedures, refer to rl78/g13 user's manual: hardware. ? serial clock select register 0 (sps0) operation clock setting select serial clock
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 18 of 43 2014.03.24 5.7.6 uart0 setup figures 5.7, 5.8, and 5.9 show the flowcharts for setting up uart0. figure 5.7 uart0 setup (1/3) r _ uart0 _ create() 1 st0 register ? 03h smr00 register ? ? ? 0 srmk0 bit ? ? 0 sremk0 bit ? ? 0 stpr10 bit ? ? 1 srpr10 bit ? ? 1 srepr10 bit ? ? 1 stop operation of channels 0 and 1. disable intst0 interrupt & clear the interrupt request flag intst0 interrupt priority level: select level 3 (lowest) intsre0 interrupt priority level: select level 3 (lowest) set sau channel 0 operation mode ? channel 0 operation clock : ck00 ? channel 0 transfer clock : division of ck00 ? start trigger source : software trigger ? detect a falling edge as a start bit ? channel 0 operation mode : uart mode ? channel 0 interrupt source : transfer end interrupt disable intsr0 interrupt & clear the interrupt request flag disable intsre0 interrupt & clear the interrupt request flag intsr0 interrupt priority level: select level 3 ( lowest )
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 19 of 43 2014.03.24 figure 5.8 uart0 setup (2/3) 1 2 scr00 register ? 8297h sdr00 register ? ce00h nfen0 register ? ? ? 0122h sau channel 0 communication operation setting ? only perform transmission ? phase with clock: type 1 ? error interrupt intsrex : masked ? output even parities ? input/output in lsb first ? stop bit length: 1 bit ? data len g th: 8 bits channel 0 transfer clock : operation clock divided by 208 rxd3 pin noise filter rxd2 pin noise filter rxd1 pin noise filter : off rxd0 pin noise filter : on clear the error flag sau channel 1 operation mode setting ? channel 1 operation clock: ck00 ? channel 1 transfer clock : division of ck00 ? start trigger source : valid edge of the rxd pin ? detect a falling edge as a start bit ? channel 1 operation mode : uart mode ? channel 1 interrupt source : transfer end interrupt
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 20 of 43 2014.03.24 figure 5.9 uart0 setup (3/3) 2 return scr01 register ? ? ? 1 sdr01 register ? ? ? ? 0 sau channel 1 communication operation setting ? only perform reception ? phase with clock: type 1 ? error interrupt intsrex : enabled ? check for even parity ? input/output in lsb first ? stop bit length: 1 bit ? data length: 8 bits channel 1 transfer clock : operation clock divided by 208 set the txd0 pin (output mode) set the pxd0 pin (input mode) prepare for the use of channel 0
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 21 of 43 2014.03.24 symbol: smr00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cks 00 ccs 00 0 0 0 0 0 0 0 0 1 0 0 md 002 md 001 md 000 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 bit 15 cks00 channel 0 operation clock (f mck ) selection 0 prescaler output clock ck00 conf igured by the sps0 register 1 prescaler output clock ck01 configured by the sps0 register bit 14 ccs00 channel 0 transfer clock (tclk) selection 0 clock obtained by dividing the operation clock f mck specified by the cks00 bit. 1 clock input from the sck pin. bits 2 and 1 md002 md001 channel 0 operation mode setting 0 0 csi mode 0 1 uart mode 1 0 simplified i 2 c mode 1 1 setting prohibited bit 0 md000 channel 0 interrupt source selection 0 transfer end interrupt 1 buffer empty interrupt caution: for details on the register setup procedures, refer to rl78/g13 user's manual: hardware. ? serial mode register 00 (smr00) interrupt source operation mode transfer clock selection f mck selection transmission channel operation mode setting
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 22 of 43 2014.03.24 symbol: scr00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txe 00 rxe 00 dap 00 ckp 00 0 eoc 00 ptc 001 ptc 000 dir 00 0 slc 001 slc 000 0 1 dls 001 dls 000 1 0 0 0 0 0 1 0 1 0 0 1 0 1 1 1 bits 15 and 14 txe00 rxe00 channel 0 operation mode setting 0 0 communication prohibited 0 1 reception only 1 0 transmission only 1 1 both transmission and reception bit 10 eoc00 error interrupt signal (intsrex (x = 0, 1)) mask availability selection 0 error interrupt intsrex is masked 1 generation of error interrupt intsrex is enabled bits 9 and 8 ptc001 ptc000 parity bit setting in uart mode transmission reception 0 0 no parity bit is output data is received without parity 0 1 0 parity is output no parity check is made 1 0 even parity is output check is made for even parity 1 1 odd parity is output check is made for odd parity bit 7 dir00 selection of data transfer order in csi and uart modes 0 input and output in msb first 1 input and output in lsb first bits 5 and 4 slc001 slc000 stop bit setting in uart mode 0 0 no stop bit 0 1 stop bit length = 1 bit 1 0 stop bit length = 2 bits 1 1 setting prohibited caution: for details on the register setup procedures, refer to rl78/g13 user's manual: hardware. ? serial communication operation setting register 00 (scr00) data length setting, data transfer order, error interrupt signal mask availability, and operation mode transmission channel communication operation setting
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 23 of 43 2014.03.24 symbol: sdr00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 x x x x x x x x bits 15 to 9 sdr00[15:9] transfer clock setting by dividing operation clock (f mck ) 0 0 0 0 0 0 0 f mck /2 0 0 0 0 0 0 1 f mck /4 0 0 0 0 0 1 0 f mck /6 0 0 0 0 0 1 1 f mck /8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 0 0 1 1 1 f mck /208 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 f mck /254 1 1 1 1 1 1 1 f mck /256 caution: for details on the register setup procedures, refer to rl78/g13 user's manual: hardware. ? serial data register 00 (sdr00) transfer clock frequency: f mck /208 ( ? 9600 hz) transmission channel transfer clock setting symbol: scr00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txe 00 rxe 00 dap 00 ckp 00 0 eoc 00 ptc 001 ptc 000 dir 00 0 slc 001 slc 000 0 1 dls 001 dls 000 1 0 0 0 0 0 1 0 1 0 0 1 0 1 1 1 bits 1 and 0 dls001 dls000 data length setting in csi mode 0 1 9-bit data length 1 0 7-bit data length 1 1 8-bit data length others setting prohibited caution: for details on the register setup procedures, refer to rl78/g13 user's manual: hardware.
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 24 of 43 2014.03.24 ? serial mode register 01 (smr01) interrupt source operation mode transfer clock selection f mck selection reception channel operation mode setting symbol: smr01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cks 01 ccs 01 0 0 0 0 0 sts 01 0 sis 010 1 0 0 md 012 md 011 md 010 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 bit 15 cks01 channel 1 operation clock (f mck ) selection 0 prescaler output clock ck00 conf igured by the sps0 register 1 prescaler output clock ck01 configured by the sps0 register bit 14 ccs01 channel 1 transfer clock (tclk) selection 0 clock obtained by dividing the operation clock f mck specified by the cks01 bit 1 clock input from the sck pin bit 8 sts01 start trigger source selection 0 only software trigger is valid 1 valid edge of the rxd pin (selected during uart reception) bit 6 sis010 control of receive data level inversion on channel 1 in uart mode 0 falling edge is detected as a start bit 1 rising edge is detected as a start bit bits 2 and 1 md012 md011 channel 1 operation mode setting 0 0 csi mode 0 1 uart mode 1 0 simplified i 2 c mode 1 1 setting prohibited bit 0 md010 channel 1 interrupt source selection 0 transfer end interrupt 1 buffer empty interrupt caution: for details on the register setup procedures, refer to rl78/g13 user's manual: hardware.
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 25 of 43 2014.03.24 ? serial communication operation setting register 01 (scr01) data length setting, data transfer order, error interrupt signal mask availability, and operation mode reception channel communication operation setting symbol: scr01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txe 01 rxe 01 dap 01 ckp 01 0 eoc 01 ptc 011 ptc 010 dir 01 0 slc 011 slc 010 0 1 dls 011 dls 010 0 1 0 0 0 1 1 0 1 0 0 1 0 1 1 1 bits 15 and 14 txe01 rxe01 channel 1 operation mode setting 0 0 communication prohibited 0 1 reception only 1 0 transmission only 1 1 both transmission and reception for uart reception, wait for 4 f clk clock cycles or more before setting ss01 to 1, after setting the rxe01 bit of the scr01 register to 1. bit 10 eoc01 error interrupt signal (intsr e1) mask availability selection 0 error interrupt intsre1 is masked 1 generation of error interrupt intsre1 is enabled bits 9 and 8 ptc011 ptc010 parity bit setting in uart mode transmission reception 0 0 no parity bit is output data is received without parity 0 1 0 parity is output no parity check is made 1 0 even parity is output check is made for even parity 1 1 odd parity is output check is made for odd parity bit 7 dir01 selection of data transfer order in csi and uart modes 0 input and output in msb first 1 input and output in lsb first bits 5 and 4 slc011 slc010 stop bit setting in uart mode 0 0 no stop bit 0 1 stop bit length = 1 bit 1 0 stop bit length = 2 bits 1 1 setting prohibited caution: for details on the register setup procedures, refer to rl78/g13 user's manual: hardware.
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 26 of 43 2014.03.24 ? serial data register 01 (sdr01) transfer clock frequency: f mck /208 ( ? 9600 hz) reception transfer clock setting symbol: sdr01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 1 1 0 bits 15 to 9 sdr01[15:9] transfer clock setting by dividing operation clock (f mck ) 0 0 0 0 0 0 0 f mck /2 0 0 0 0 0 0 1 f mck /4 0 0 0 0 0 1 0 f mck /6 0 0 0 0 0 1 1 f mck /8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 0 0 1 1 1 f mck /208 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 f mck /254 1 1 1 1 1 1 1 f mck /256 caution: for details on the register setup procedures, refer to rl78/g13 user's manual: hardware. symbol: scr01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txe 01 rxe 01 dap 01 ckp 01 0 eoc 01 ptc 011 ptc 010 dir 01 0 slc 011 slc 010 0 1 dls 011 dls 010 0 1 0 0 0 1 1 0 1 0 0 1 0 1 1 1 bits 1 and 0 dls011 dls010 data length setting in csi mode 0 1 9-bit data length 1 0 7-bit data length 1 1 8-bit data length others setting prohibited caution: for details on the register setup procedures, refer to rl78/g13 user's manual: hardware.
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 27 of 43 2014.03.24 symbol: so0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 cko 03 cko 02 cko 01 cko 00 0 0 0 0 so 03 so 02 so 01 so 00 0 0 0 0 x x x x 0 0 0 0 x x x 1 bit 0 so00 channel 0 serial data output 0 serial data output value is ?0? 1 serial data output value is ?1? caution: for details on the register setup procedures, refer to rl78/g13 user's manual: hardware. ? serial output register 0 (so0) initial output: 1 initial output level setting symbol: soe0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 soe 03 soe 02 soe 01 soe 00 0 0 0 0 0 0 0 0 0 0 0 0 x x x 1 bit 0 soe00 channel 0 serial output enable/stop 0 serial communication output is stopped 1 serial communication output is enabled caution: for details on the register setup procedures, refer to rl78/g13 user's manual: hardware. ? serial output enable register 0 (soe0) output enable enabling of data output on target channel
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 28 of 43 2014.03.24 ? port register 1 (p1) ? port mode register 1 (pm1) port setting for each of transmit data and receive data. symbol: p1 7 6 5 4 3 2 1 0 p17 p16 p15 p14 p13 p12 p11 p10 x x x x x 1 x x bit 2 p12 output data contro l (in output mode) 0 0 is output 1 1 is output caution: for details on the register setup procedures, refer to rl78/g13 user's manual: hardware. symbol: pm1 7 6 5 4 3 2 1 0 pm17 pm16 pm15 pm 14 pm13 pm12 pm11 pm10 x x x x x 0 1 x bit 2 pm12 p12 i/o mode selection 0 output mode (output buffer is on) 1 input mode (output buffer is off) bit 1 pm11 p11 i/o mode selection 0 output mode (output buffer is on) 1 input mode (output buffer is off) caution: for details on the register setup procedures, refer to rl78/g13 user's manual: hardware. port setting
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 29 of 43 2014.03.24 5.7.7 main function figures 5.10 and 5.11 show the flowchart for the main function. figure 5.10 main function (1/2) main() r_uart0_receive() r_uart0_start() 5 no yes 3 4 no yes no yes r_uart0_send() no yes no yes r_uart0_send() uart0 reception status initialization function uart0 operation start function move to halt mode disable reception interrupt reception error detected? framing error? uart0 d a t a t ransm i ss i on function transmission completed? parity error? uart0 d a t a t ransm i ss i on function transmission completed? srmk0 bit ? ? 1 specify the uart0 receive buffer and the number of pieces of data (1)
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 30 of 43 2014.03.24 figure 5.11 main function (2/2) 3 4 no yes no yes r_uart0_send() r_uart0_send() r_uart0_send() r uart0 send () 5 no yes r_uart0_receive() parity error? = ?t? = ?t? other than ?t? and ?t? transmission completed? argument: ?ok? argument: ?ok? argument: ?uc? uart0 d a t a t ransm i ss i on function uart0 d a t a t ransm i ss i on function uart0 reception status initialization function what is the receive data? uart0 d a t a t ransm i ss i on function uart0 d a t a t ransm i ss i on function transmission completed? enable reception interrupt srmk0 bit ? ? 0
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 31 of 43 2014.03.24 5.7.8 uart0 reception status initialization function figure 5.12 shows the flowch art for the uart0 r eception status initialization function. figure 5.12 uart0 reception status initialization function r_uart0_receive() return yes no set the initial status value to ok number of pieces of data = 0? initialize the receive data number counter set the number of pieces of receive data initialize the receive data pointer set the status to error set the return value to the status
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 32 of 43 2014.03.24 5.7.9 uart0 operation start function figure 5.13 shows the flowchart for the uart0 operation start function. figure 5.13 uart0 operation start function r_uart0_start() return enable transmission interrupt enable reception interrupt enable reception error interrupt set the txd0 output level enable uart0 output enable uart0 operation stif0 bit ? ? 0 srif0 bit ? ? 0 sreif0 bit ? ? 0 so0.0 bit ? 1 soe0.0 bit ? 1 ss0.0 bit ? ?
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 33 of 43 2014.03.24 ? interrupt request flag register (if0h) clear the interrupt request flag ? interrupt mask flag register (mk0h) cancel interrupt mask interrupt setting symbol: if0h 7 6 5 4 3 2 1 0 sreif0 tmif01h srif0 csiif01 iicif01 stif0 csiif00 iicif00 dmaif1 dmaif0 sreif2 tmif11h srif2 csiif21 iicif21 stif2 csiif20 iicif20 0 0 0 x x x x x bit 7 sreif0 interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status bit 6 srif0 interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status bit 5 stif0 interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status caution: for details on the register setup procedures, refer to rl78/g13 user's manual: hardware.
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 34 of 43 2014.03.24 symbol: mk0h 7 6 5 4 3 2 1 0 sremk0 tmmk01h srmk0 csimk01 iicmk01 stmk0 csimk00 iicmk00 dmamk1 dmamk0 sremk2 tmmk11h srmk2 csimk21 iicmk21 stmk2 csimk20 iicmk20 0 0 0 x x x x x bit 7 sremk0 interrupt processing control 0 enables interrupt processing. 1 disables interrupt processing. bit 6 srmk0 interrupt processing control 0 enables interrupt processing. 1 disables interrupt processing. bit 5 stmk0 interrupt processing control 0 enables interrupt processing. 1 disables interrupt processing. caution: for details on the register setup procedures, refer to rl78/g13 user's manual: hardware.
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 35 of 43 2014.03.24 symbol: ss0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ss03 ss02 ss01 ss00 0 0 0 0 0 0 0 0 0 0 0 0 x note x 1 note 1 bits 3 to 0 ss0n channel n operation start trigger 0 trigger operation is not performed 1 se0n is set to 1, and a communication wait state is entered. note for uart reception, wait for 4 f clk clock cycles or more before setting ss0n to 1, after setting the rxe0n bit of the scr0n register to 1. caution: for details on the register setup procedures, refer to rl78/g13 user's manual: hardware. ? serial channel start register 0 (ss0) operation start transition to communication wait state
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 36 of 43 2014.03.24 5.7.10 intsr0 interrupt service routine figure 5.14 shows the flowchart for the intsr0 interrupt service routine. figure 5.14 intsr0 interrupt service routine r_uart0_interrupt_receive() return r_uart0_callback_receiveend() yes yes no no read receive data within the specified number of pieces of data? store the received data update the pointer and the counter data setting completed? uart0 receive data classification function
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 37 of 43 2014.03.24 5.7.11 uart0 receive data classification function figure 5.15 shows the flowch art for the uart0 receive data classification function. figure 5.15 uart0 receive data classification function return clear the reception error flag r_uart0_callback_receiveend()
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 38 of 43 2014.03.24 5.7.12 uart0 data transmission function figure 5.16 shows the flowchart for the uart0 data transmission function. figure 5.16 uart0 data transmission function r_uart0_send() return no yes set the status to the initial value ok stmk0 bit ? 1 number of pieces of data = 0? set the status to error initialize the transmit data pointer set the number of pieces of transmit data mask transmission interrupt transmit the first data update the transmit data p ointer update the number of pieces of transmit data cancel transmission interrupt mask set the return value to the status txd0 register ? data stmk0 bit ? 0
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 39 of 43 2014.03.24 5.7.13 uart0 reception error interrupt function figure 5.17 shows the flowchart for the uart0 reception error interrupt function. figure 5.17 uart0 reception error interrupt function r_uart0_interrupt_error() return r_uart0_callback_error() buffer ? rxd0 sir01 register ?
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 40 of 43 2014.03.24 5.7.14 uart0 reception error classification function figure 5.18 shows the flowch art for the uart0 r eception error classification function. figure 5.18 uart0 reception error classification function r_uart0_callback_error() return error flag setting
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 41 of 43 2014.03.24 5.7.15 intst0 interrupt service routine figure 5.19 shows the flowchart for the intst0 interrupt service routine. figure 5.19 intst0 interrupt service routine r_uart0_interrupt_send return no yes r_uart0_callback_sendend() is there any data left? transmit data update the pointer and the counter uart0 transmission end processing function
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 42 of 43 2014.03.24 5.7.16 uart0 transmission end processing function figure 5.20 shows the flowchart for the uart0 transmission end processing function. figure 5.20 uart0 transmission end processing function r_uart0_callback_sendend() return set transmission end flag
rl78/g13 serial array un it (uart communication) r01an0459ej0200 rev. 2.00 page 43 of 43 2014.03.24 6. sample code the sample code is available on the renesas electronics website. 7. documents for reference rl78/g13 user's manual: hardware rev.0.07 (r01uh0146ej0007) rl78 family user's manual: software rev.1.00 (r01us0015ej0100) (the latest versions of the documents are available on the renesas electronics website.) technical updates/technical brochures (the latest versions of the documents are available on the renesas electronics website.) website and support renesas electronics website ? http://www.renesas.com/index.jsp inquiries ? http://www.renesas.com/contact/
a-1 revision record rl78/g13 serial array unit (uart communication) rev. date description page summary 1.00 2011.09.30 ? first edition issued 2.00 2014.03.24 5 table 2.1: added e2studio and iar version information 12 figure 5.1, figure 5.2: added note figure 5.2: fixed typo in a function name 13 figure 5.3: fixed typo in the function name all trademarks and registered trademarks are t he property of their respective owners.
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the relevant s ections of the manual. if the descriptions under general precautions in the handling of mpu/ mcu products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. handling of unused pins ? handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on ? the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied un til the power reaches the le vel at which resetting has been specified. 3. prohibition of access to reserved addresses ? access to reserved addresses is prohibited. ? the reserved addresses are provided for the possible future expansion of functions. do not access these addresses; the correct oper ation of lsi is not guaranteed if they are accessed. 4. clock signals ? after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program ex ecution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full st abilization of the clock signal . moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products ? before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbers, implement a system-evaluation test for each of the products.
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